Computers use memory devices for the storage and retrieval of information. These memory devices are often mounted on a memory module to expand the memory capacity of a computer. Sockets on a main board accommodate those memory modules also known as single inline memory modules (“SIMMs”) or dual in-line memory modules (“DIMMs”).
FIG. 1 is a diagram schematically illustrating a standard memory interface system overview in accordance with a prior art. The system 100 includes a processor 102, a memory controller 104, and a memory module 106. The processor 102 communicates with the memory controller 104 with an address bus 108, a control signal bus 110, and a data bus 112. The memory controller 104 communicates with the memory module 106 with a controller address bus 114, a controller control signal bus 116, and a controller data bus 118. Common system implementations 100 have typically two memory chip selects routed per socket. Common memory module 106 may have two chip selects (one per rank) or four chip selects (two per rank). In one implementation, each chip select from the controller is connected to the corresponding chip select on the memory module. In the second implementation, each chip select from the controller is connected to the two chip selects (those that control one rank) on the memory module. The system chip select signals control individual memory modules ranks. The memory module 106 is coupled to the memory controller 104 through a memory socket.
Standard memory modules such as memory module 106 have either one rank or two rank of memory devices. Each memory device comes in a variety of configurations and families such as 128 Mbit, 256 Mbit, 512 Mbit, and 1024 Mbit double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) families. Each of these families is further divided into three distinct flavors such as x4, x8, and x16 data bits. For example, a single 128 Mbit DDR SDRAM family comes in three flavors of:
32M×4 (32 Mega cell of 4-bit each=32M×4-bit=128 Mbit)
16M×8 (16 Mega cell of 8-bit each=16M×8-bit=128 Mbit)
8M×16 (8 Mega cell of 16-bit each=8M×16-bit=128 Mbit)
The example above illustrates that all three different data bits flavors result in the same density of 128 Mbit. As the number of data bits doubles the cell numbers decrease by half. One can build memory modules with similar densities using different data bits flavors.
One method of building a 512 M Byte standard memory module with error correction code (“ECC”) (64-bit data plus 8-bit ECC=72-bit) includes using 256 Mbit density families of 32M×8 to achieve the density of 512 M Byte as follow:
Rank 0=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256 M Byte.
Rank 1=9×(32M×8) devices=32M×72-bit which equates to 32M×8 Bytes+1 Byte of ECC. This yields a total density of 32M×8 Bytes=256 M Byte.
Therefore, a two rank memory module with 18 device placements will achieve the 512 M Byte density. Furthermore, it should be noted that a standard DDR 184-pin memory module can only fit nine thin shrink small outline package (“TSSOP”) placements per side, or a total of 18 placements of TSSOP per module, considering both front and back sides based on a standard defined height limits by Joint Electron Device Engineering Council (“JEDEC”).
Therefore, a two rank memory module with 18 device placements will achieve the 512M Byte density. Furthermore, it should be noted that a standard DDR 184-pin memory module can only fit nine TSSOP placements per side, or a total of 18 placements of TSSOP per module, considering both front and back sides based on a standard defined height limits by JEDEC.
Because memory devices with lower densities are cheaper and more readily available, it may be advantageous to build the above same density memory module using lower densities devices. However, in order to achieve a density of, for example, 512 M Bytes using 128 Mbit density of 16M×8 instead, the memory module needs four ranks configured as follows:
Rank 0=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
Rank 1=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
Rank 2=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
Rank 3=9×(16M×8) devices=16M×72-bit which equates to 16M×8 Bytes+1 Byte of ECC. This would give us a total density of 16M×8 Bytes=128 M Byte.
In order to achieve the above configuration, 4 rows of 9 devices each, totaling 36 placements, are required. As mentioned above, on a standard 184-pin DDR memory module, there is only enough space for 18 TSSOP devices.
The only solution would be, to stack two memory devices together to achieve an extra rank on the same placement space. Although this would solve the placement problem of 36 TSSOP devices, the memory module would still possess four memory ranks. As explained earlier, all standard memory modules have only two chip select signals per memory socket routed. Therefore, such memory module would not be viable.
A need therefore exists for a transparent four rank memory module fitting into a memory socket having two chip select signals routed. A primary purpose of the present invention is to solve these needs and provide further, related advantages.